1. Field of the Invention
The present invention relates generally to a method for producing a memory cell arrangement, and particularly to a memory cell having vertical transistors.
2. Description of the Related Art
In order to store large volumes of data, for example for DP (data processing) applications or for the digital storage of music or images, use is mainly made at present of memory systems which have mechanically movable parts such as, for example, hard disk memories, floppy disks or compact discs. The moved parts are subject to mechanical wear. Furthermore, they require a comparatively large volume and permit only slow data access. Moreover, since they are sensitive to vibrations and position and have a comparatively high power consumption for their operation, these memory systems can be used is mobile systems only to a limited extent.
In order to store relatively small volumes of data, semiconductor-based read-only memories are known. These are often realised as a planar integrated silicon circuit is which MOS transistors are used as memory cells. The transistors are selected via the gate electrode, which is connected to the word lice. The input of the MOS transistor is connected to a reference line and the output is connected to a bit line. During the read operation, it is assessed whether or not a current is flowing through the transistor. The logic values zero and one are assigned correspondingly. The storage of zero and one is effected in technical terms is that no MOS transistor is produced or no conductive connection to the bit lice is realised in memory cells is which the logic value assigned to the state xe2x80x9cno current flow through the transistorxe2x80x9d is stored. As an alternative, MOS transistors which have different threshold voltages due to different dopant concentrations is the channel region can be realised for the two logic values.
These semiconductor-based memories permit random access to the stored information. The electrical power required to read the informatics is distinctly less than is the case of the abovementioned memory systems having mechanically movable parts. Since no movable parts are required, mechanical wear and sensitivity to vibrations are no longer a problem here either. Semiconductor-based memories can therefore be used for mobile systems as well.
The silicon memories described generally have a planar structure. A minimum area requirement thus becomes necessary for each memory cell and is 4 F2 in the most favourable case, F being the smallest structure size that can be produced with the respective technology.
A read-only memory cell arrangement whose memory cells comprise MOS transistors is disclosed in German Patent document DE 42 14 923 A1. These MOS transistors are arranged along trenches in such a way that a source region adjoins the bottom of the trench, a drain region adjoins the surface of the substrate and a channel region adjoins the side and bottom of the trench both vertically with respect to the surface of the substrate and parallel to the surface of the substrate. The surface of the channel region is provided with a gate dielectric. The gate electrode is designed as a side covering (spacer). The logic values zero and one are differentiated by different threshold voltages, which are effected by channel implantation. During the channel implantation, the implanting ions impinge on the surface of the respective trench at as angle such that implantation is deliberately effected only along one side due to shading effects of the opposite side. In this memory cell arrangement, the word lines run as spacers, along, the sides of the trenches.
Japanese Patent document JP-A 4-226071 discloses a further memory cell arrangement, which comprises vertical MOS transistors arranged on the sides of trenches as memory cells. In this case, diffusion regions which in each case form the source/drain regions of the vertical MOS transistors run on the bottom of trenches and between adjacent trenches. The word lines, which comprise the gate electrodes of the vertical MOS transistors, run perpendicularly to the trenches. The threshold voltage of the vertical MOS transistors is sat by means of angled implantation.
U.S. Pat. No. 4,663,644 discloses a memory cell arrangement whose memory cells comprise vertical MOS transistors. These vertical MOS transistors are each arranged on the aides of trenches. The word lines, which each comprise the gate electrodes of the vertical MOS transistors, are arranged is the trenches. Two word lines are arranged is each trench. The bit lines are realised as conductor tracks on the surface of the substrate. The contact between the bit lines and the respective source/drain regions which adjoin the surface of the substrate is realised via a contact hole. The source/drain regions which adjoin the bottom of the trenches are realised as a continuous doped layer and are put at the reference potential. In this memory cell arrangement, the information is stored is the form of threshold voltages, having different levels, of the MOS transistors. The different threshold voltages are realised by different dopant concentrations in the channel region of the MOS transistors. In order to form as increased dopant concentration is the channel region, a doped layer is deposited and is structured in such a way that sides in which increased dopant concentrations are to be formed remain covered by the structured dopant layer. The channel regions having as increased dopant concentration are formed by outdiffusion of the structured dopant layer.
In order to increase the effective storage density, it has furthermore been proposed (see, for example, the publication by Yasushi Kubota, Shinji Toyoyama, Yoji Kanic, Shuhei Tsuchimoto xe2x80x9cProposal of New Multiple-Valued Mask-ROM Designxe2x80x9d IEICE Trans. Electron Vol. E77, p. 601, April 1994), to program a semiconductor memory arrangement having planar MOS transistors in the sense of multi-value logic. This procedure is also referred to as multi-level programming. In this case, the MOS transistors are produced in such a way that they have four different threshold voltage values depending on the stored information. Each of the threshold voltage values is then assigned two logic values, that is to say xe2x80x9c0xe2x80x9d and xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d and xe2x80x9c1xe2x80x9d. In this way, the effective storage density rises by a factor of two since two logic values are stored is each memory call without the area of the memory cell changing as a result of this. The different threshold voltage values are realised by different channel dopings. Masked implantation is carried out for each threshold voltage value. Four additional masks are therefore necessary for multi-level programming.
The problem underlying the invention is that of specifying a semiconductor-based memory cell arrangement in which as increased storage density is achieved and which can be produced with few production steps and a high yield. Furthermore, it is intended to specify a method for the production of such a memory cell arrangement.
The present invention solves the foregoing problems by a method for the production of a memory cell arrangement, in which strip-like trenches which essentially run in parallel are formed in a main area of a substrate which comprises, at least in the region of the main area, semiconductor material which is doped by a first conductivity type, in which MOS transistors which are vertical with respect to the main area are formed on the sides of the trenches, act as memory cells and have at least three different threshold voltage values depending on the stored information, in which a first threshold voltage value is realized by the thickness of the gate dielectric and a second and a third threshold voltage value are realized by different channel dopings.
In a preferred method, strip-like, doped regions, which are doped by a second conductivity type opposite to the first, are formed on the bottom of the trenches and on the main area between adjacent trenches, in which an insulating layer is applied, in which a first mask which has first openings is produced on the insulating layer, in which the insulating layer is structured by anisotropic etching, while using the first mask, in such a way that the sides of trenches are at least partially exposed in the region of the first openings, in which the exposed sides are doped, in which a second mask which has second openings is produced on the insulating layer, in which the insulating layer is structured by anisotropic etching, while using the second mask, in such a way that the sides of trenches are at least partially exposed in the region of the second openings, as well, in which a gate dielectric is formed on the sides of the trenches, and in which word lines are formed which run transversely with respect to the trenches.
In such a method, the insulating layer may fill the trenches, and the sides of the trenches may be essentially completely exposed in the region of the first and of the second openings. The sides may be doped by angled implantation. The implantation is carried out at any angle of inclination in the range between 20xc2x0 and 30xc2x0 and/or xe2x88x9220xc2x0 and xe2x88x9230xc2x0 with respect to the normal to the main area. In one embodiment, the sides are doped by diffusion. The trenches are provided with spacers, the strip-like, doped regions are formed by implantation in which the spacers on the sides of the trenches have a masking action, the spacers are removed after the formation of the strip-like, doped regions.
In the memory cell arrangement according to the present invention, memory cells which each comprise an MOS transistor which is vertical with respect to the main area are provided in a substrate. A substrate made of monocrystalline silicon or the silicon layer of an SOI substrate is preferably used as the substrate. The vertical MOS transistors each have one of at least three threshold voltage values depending on the stored information. The memory cell arrangement is programmed in the sense of multi-value logic.
One of the different threshold voltage values is realised by virtue of the fact that the corresponding MOS transistors have a gate dielectric having a thickness differing from the other MOS transistors. The thickness of the gate dielectric is preferably greater than in the other MOS transistors, with the result that a thick oxide transistor is formed. The remaining threshold voltage values are realised by different channel dopings.
2n threshold voltages, where n greater than 1, are preferably realised since n logic values are then stored is each memory cell.
Strip-like trenches which essentially run in parallel are preferably provided is the substrate. Strip-like doped regions, which are doped by a second conductivity type which is opposite to the first, are arranged on the bottom of the trenches and on the main area between adjacent trenches. Gate dielectrics are is each case arranged on the sides of the trenches. Word lines are provided which run transversely with respect to the trenches and comprise gate electrodes for the vertical MOS transistors is the region of the sides of the trenches. The vertical MOS transistors are in each case formed by two strip-like, doped regions adjoining the same side of one of the trenches, which doped regions act as source/drain region, the trench side arranged in between together with the gate dielectric and the part of one of the word lines arranged thereabove. The strip-like doped regions are used as bit or reference lines during operation of the memory cell arrangement.
The spacing between adjacent trenches is preferably chorea is such a way that it is essentially equal to the width of the trenches. The spacing between adjacent word lines is likewise chosen to be equal to the width of the word lines. If the width of the trenches and the width of the word lines are chorea to correspond to the minimum structure width F is the respective technology, this produces a space requirement of 2 F2 for the memory cell. If the four MOS transistors have four different threshold voltage values, then two logic values, that is to say two bite, are stored is each memory cell. The space requirement per bit is then F2. If a minimum structure width of F=0.4 xcexcm is takes as a basis and if the four MOS transistors have four different threshold voltage values, then a storage density of about 6.2 bits/xcexcm2 is achieved in the memory cell arrangement.
In order to produce the memory cell arrangement according to the present invention, strip-like trenches which essentially run is parallel are preferably formed in a main area of a substrate. Vertical MOS transistors are formed on the sides of the trenches with respect to the main area, which transistors act as memory cells and have at least three different threshold voltage values depending on the stored information.
Strip-like, doped regions, which are doped by a second conductivity type which is opposite to the first, are preferably formed on the bottom of the trenches and on the main area between adjacent trenches. An insulating layer is subsequently applied. A first mask which is made, for example, of photoresist and has first openings is produced on the insulating layer. The insulating layer is structured using the first mask such that the sides of the trenches are at least partially exposed is the region of the first openings. The exposed sides are doped.
A second mask which is made, for example, of photoresist and has second openings is produced on the insulating layer. The insulating layer is structured using the second mask such that the sides of the trenches are at least partially exposed in the region of the second openings.
Outside the first and second openings, the sides remain covered by the structured insulating layer. The structured insulating layer acts as a thick gate dielectric is this region. A gate dielectric is formed on the sides is the region of the first and second openings.
Word lines which run transversely with respect to the trenches are subsequently formed.
The threshold voltage value is set by the doping of the exposed sides is the region of the first openings, by the doping of the substrate is the region of the second openings, and by the thickness of the insulating layer outside the first and second openings.
In order to produce more than three threshold voltage values, prior to the formation of the second mask, further masks are formed, structurings of the insulating layer are carried out and exposed aides are doped.
Since one of the threshold voltage values is set by way of the thickness of the structured insulating layer, the number of masks required for programming is smaller by one than the number of threshold voltage values.
The exposed aides are preferably doped by angled implantation. The implantation is preferably carried out at an angle of inclination is the range between 20xc2x0 and 30xc2x0 with respect to the normal to the main area. Angles of inclination of this type are provided as standard in many implantation installations is order to avoid the channeling effect.
As an alternative, the exposed sides are produced by outdiffusion of a doped layer. The doped layer is applied over the whole area above the structured insulating layer. The doped layer is preferably formed from doped glass, doped polysilicon or doped amorphous silicon. The use of doped glass has the advantage that the doped layer can in this case be removed selectively with respect to the substrate.
The insulating layer is preferably applied with a layer thickness such that it fills the trenches. The surface of the substrata is exposed prior to the formation of the first mask. The respective sides of the trenches are essentially completely exposed during the structuring of the insulating layer. A planar structure is obtained by the filling of the trenches. Focus problems are consequently avoided during the formation of the masks for the purpose of structuring the insulating layer. Furthermore, the variation in the individual threshold voltage values is reduced.
The trenches are preferably formed by anisotropic etching using a trench mask.
The strip-like, doped regions on the bottom of the trenches and on the main area between adjacent trenches are preferably produced by as implantation after the trench formation and after the removal of the trench mask. In this case, it is advantageous to provide the sides of the trenches with spacers prior to the implantation, which spacers have a masking action during the implantation. These spacers are subsequently removed. The formation of the trenches and of the strip-like, doped regions requires only one mask.
As an alternative, the strip-like, doped regions can be produced by producing A doped region on the main area, which doped region covers the entire memory cell array, before the formation of the trenches. When the trenches are opened, this doped region is subdivided into the strip-like, doped regions on the main area. The strip-like, doped regions on the bottom of the trenches are produced by ion implantation after the trenches have been opened. When using a trench mask, it is advantageous here to leave it as a mask on the main area during the implantation.
The insulating layer is preferably structured by anisotropic etching. However, the insulating layer can also be structured by combined isotropic and anisotropic etching. The etching takes place selectively with respect to the substrate.